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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3747
7400 PIXELS CCD LINEAR IMAGE SENSOR
The PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
* Valid photocell * Photocell pitch * Photocell size * Resolution * Data rate * Output type * High sensitivity * Low image lag * Power supply * On-chip circuits : : 7400 pixels : 4.7 m : 4.7 x 4.7 m
2
: 24 dot/mm (600 dpi) A3 (297 x 420 mm) size (shorter side) : 44 MHz MAX. (22 MHz/1 output) : 2 outputs in phase : 19.0 V/lx*s TYP (Light source: Daylight color fluorescent lamp) . : 1 % MAX. : +12 V
* Drive clock level : CMOS output under 5 V operation : Reset feed-through level clamp circuits Voltage amplifiers
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
PD3747D
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14892EJ1V0DS00 (1st edition) Date Published June 2000 NS CP (K) Printed in Japan
(c)
2000
S7399
S7400
D134
D135
D140
D33
S1
S2
2
BLOCK DIAGRAM
CP
20
GND 21
GND 11
2L
18
2
14
1
13
VOUT2 (Even)
22
CCD analog shift register Transfer gate Photocell Transfer gate 12
***
***
TG
Data Sheet S14892EJ1V0DS00
VOUT1 (Odd)
1
CCD analog shift register
2 VOD
4
5
9
10
R
2L
1
2
PD3747
PD3747
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) * PD3747D
Output signal 1 (Odd) Output drain voltage No connection Reset gate clock Last stage shift register clock 2 No connection No connection No connection Shift register clock 1 Shift register clock 2 Ground
VOUT1 VOD NC
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VOUT2 GND
Output signal 2 (Even) Ground Reset feed-through level clamp clock No connection Last stage shift register clock 2 No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock
CP
NC
R
2L
NC NC NC
2L
NC NC NC
1
2
GND
2 1 TG
PHOTOCELL STRUCTURE DIAGRAM
3.2 m
1.5 m
4.7 m
Channel stopper
Aluminum shield
Data Sheet S14892EJ1V0DS00
3
PD3747
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V 1, V 2, V 2L V R V CP V TG TA Tstg Symbol Ratings -0.3 to +14 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +55 -40 to +100 Unit V V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V 1H, V 2H, V 2LH V 1L, V 2L, V 2LL V RH V RL V CPH V CPL V TGH V TGL 2f R Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 1 TYP. 12.0 5.0 0 5.0 0 5.0 0 5.0 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.5 +0.5 44 Unit V V V V V V V V V MHz
4
Data Sheet S14892EJ1V0DS00
PD3747
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 12 V, f R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Image lag Offset level
Note 1 Note 2
Symbol Vsat SE PRNU ADS DSNU PW ZO RF IL VOS td RI TTE
Test Conditions
MIN. 1.5 - - - - - -
TYP. 2.0 0.10 5 0.5 8.0 350 0.2 19.0 0.5 4.7 14 1.0 98 550 250 1000 +300 2.0 8.0 8.0
MAX. - - 10 3.0 14.0 600 0.3 24.7 1.0 5.7 - 4.0 - - - - +900 - - -
Unit V lx*s % mV mV mW k V/lx*s % V ns % % nm times times mV mV mV mV
Daylight color fluorescent lamp VOUT = 500 mV Light shielding Light shielding
Daylight color fluorescent lamp VOUT = 500 mV
13.3 - 3.7 - 0 94 -
Output fall delay time Register imbalance
VOUT = 500 mV VOUT = 500 mV VOUT = 1 V, data rate = 44 MHz
Total transfer efficiency Response peak Dynamic range
Note 1
DR1 DR2
Vsat/DSNU Vsat/ bit Light shielding Light shielding, bit clamp mode Light shielding, line clamp mode VOUT = 500 mV, bit clamp mode
- - -300 - - -
Reset feed-through noise Random noise
RFTN
bit line shot
Shot noise
Notes 1. Refer to TIMING CHART 2, 3. . 2. When the fall time of 2L (t2') is the TYP value (refer to TIMING CHART 2, 3). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
Data Sheet S14892EJ1V0DS00
5
PD3747
INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C 1 Pin name Pin No. 9 13 Shift register clock pin capacitance 2 C 2 MIN. - - - - - - - - - TYP. 250 250 250 250 10 10 10 10 100 MAX. 300 300 300 300 20 20 20 20 150 Unit pF pF pF pF pF pF pF pF pF
1 2 2L R CP TG
10 14
Last stage shift register clock pin capacitance
C L
5 18
Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
C R C CP C TG
4 20 12
6
Data Sheet S14892EJ1V0DS00
TIMING CHART 1
TG
1
2
2L
R
CP (Bit clamp mode) CP (Line clamp mode)
Note Note
7531
7533
7535
7537
7539 7540
VOUT1
7532
7534
7536
7538
VOUT2
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocell (7400 pixels)
7542
126
128
130
132
134
136
138
30
32
34
36
2
4
6
7541
125
127
129
131
133
135
137
29
31
33
35
1
3
5
Data Sheet S14892EJ1V0DS00
PD3747
Invalid photocell (6 pixels)
Note Set the R and CP to low level during this period.
7
PD3747
TIMING CHART 2 (Bit clamp mode)
t1 t2
1
90% 10% 90% 10% t1' t2'
2
2L
90% 10% t4 t3 t5 t6
R
90% 10% t10 t8 t7 t9 t11
CP
90% 10% + td RFTN RFTN - 10% VOS
VOUT1, 2
Symbol t1, t2 t1', t2' t3 t4, t5 t6 t7 t8, t9 t10 t11
MIN. 0 0 10 0 0 5 0 t3 0
TYP. 50 5 125 5 125 125 5 125 250
MAX. - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns
8
Data Sheet S14892EJ1V0DS00
PD3747
TIMING CHART 3 (Line clamp mode)
t1 t2
1
90% 10% 90% 10% t1' t2'
2
2L
90% 10% t4 t3 t5 t12
R
90% 10%
CP
"L" + td RFTN RFTN - 10% VOS
VOUT1, 2
Symbol t1, t2 t1', t2' t3 t4, t5 t12
MIN. 0 0 10 0 5
TYP. 50 5 125 5 250
MAX. - - - - -
Unit ns ns ns ns ns
Data Sheet S14892EJ1V0DS00
9
PD3747
TIMING CHART 4 (Bit clamp mode, Line clamp mode)
t14 90% 10% t16 t13 t15
TG
1
90%
2, 2L
t4 t3 t5
t17
t6
R
90% 10% t10 t8 t7 t9 t11
CP
Note
90% 10%
Note Set the R and CP to low level during this period.
Symbol t3 t4, t5 t6 t7 t8, t9 t10 t11 t13 t14, t15 t16, t17
MIN. 10 0 0 5 0 t3 0 1000 0 200
TYP. 125 5 125 125 5 125 250 1500 50 300
MAX. - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns
1, 2 cross points
1
1, 2L cross points
1
2 V or more
2 V or more
2 V or more
2
2L
0.5 V or more
Remark Adjust cross points of ( 1, 2) and ( 1, 2L) with input resistance of each pin.
10
Data Sheet S14892EJ1V0DS00
PD3747
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
x x x 100 x: maximum of xj - x
7400 j=1
PRNU (%) =
xj
VOUT
x=
7400
xj: Output voltage of valid pixel number j
Register dark DC level
x x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7400 j=1
dj
dj: Dark signal of valid pixel number j
ADS (mV) =
7400
Data Sheet S14892EJ1V0DS00
11
PD3747
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV): maximum of dj - ADS j = 1 to 7400 dj: Dark signal of valid pixel number j
VOUT ADS Register dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (%) =
V1 x 100 VOUT
9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
(V2j - 1 - V2j)
j=1
2
1 n
Vj
j=1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel
12
Data Sheet S14892EJ1V0DS00
PD3747
10. Random noise : Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding).
100
(mV) =
i=1
(Vi - V)
100
2
, V=
1
100
100 i = 1
Vi
Vi : A valid pixel output signal among all of the valid pixels
VOUT
V1 V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 11. Shot noise : shot Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. This includes the random noise. The formula is the same with that of random noise.
Data Sheet S14892EJ1V0DS00
...
line 100
...
13
PD3747
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
8
2
4 1
Relative Output Voltage
2
1
0.5
Relative Output Voltage
0.25
0.2
0.1 0 10 20 30 40 50 Operating Ambient Temperature TA (C)
0.1 1 5 Storage Time (ms) 10
SPECTRAL RESPONSE CHARACTERISTIC (TA = +25C)
100
80
Response Ratio (%)
60
40
20
0 400 600 800 Wavelength (nm) 1000 1200
14
Data Sheet S14892EJ1V0DS00
PD3747
APPLICATION CIRCUIT EXAMPLE
+5 V +12 V +5 V
+ 10 F/16 V 0.1 F + 0.1 F 47 F/25 V 1 2 3 4 5 6 7 8 2 2 9 10 11
PD3747
B1 VOUT1 VOD NC VOUT2 GND 22 21 20 19 18 17 16 15 14 13 12 10 2 2 47 47 B2
+ 0.1 F 10 F/16 V
CP
NC
CP
R 2L
47 47
R 2L
NC NC NC
2L
NC NC NC
2L
1 2
1 2
GND
2
2 1
1
TG
TG
Remarks 1.
It is recommended that pins 5 and 18 ( 2L) are separately driven a driver other than that of pins 10, 14 ( 2).
2.
The inverters shown in the above application circuit example are the 74AC04.
B1, B2 EQUIVALENT CIRCUIT
+12 V
4.7 k 110 CCD VOUT 47 2SA1005
47 F/25V
+
2SC945
1 k
Data Sheet S14892EJ1V0DS00
15
PD3747
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400))
(Unit : mm)
The 1st valid pixel 3.2 0.3
1
42.2 0.25 48.6 0.5
1.600.25
9.650.3
10.16
3
(1.95)
2.38 0.3 1.02 0.15 0.46 0.06 25.4 2.54 (5.37) 4.680.5 4.330.5
0~10
2
0.250
.05
Name Glass cap
Dimensions 47.5x9.25x0.7
Refractive index 1.5
1 1st valid pixel Center of pin 1 2 Photosensitive surface of CCD chip 3 Photosensitive surface of CCD chip
Bottom of package Top of glass cap
22D-1CCD-PKG10
16
Data Sheet S14892EJ1V0DS00
PD3747
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E). Type of Through-hole Device
PD3747D : CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
Process Partial heating method Conditions Pin temperature : 300C or below, Heat time : 3 seconds or less (per pin)
Data Sheet S14892EJ1V0DS00
17
PD3747
[MEMO]
18
Data Sheet S14892EJ1V0DS00
PD3747
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14892EJ1V0DS00
19
PD3747
* The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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